[CLUE-Tech] Celron v. PIII on Linux

[Mike Staver]

I'm not 100% on this, but I think it's an Intel invented optimized set
of short cpu instructions and problems can be written to use.  I know
for a fact that P4 has SSE, SSE2, and MMX.  The P III has SSE and MMX I
think, couldn't tell you if the celeron does or not.  The new Athlon XP
has SSE, MMX, and 3Dnow technology that helps with games and stuff.  I'm
not sure if it helps other programs that much though.

Randy Arabie wrote:
> 
> On Sun, 24 Feb 2002, Mike Staver wrote:
> 
> > Not to mention Pentium III has 133 FSB in the newer models, while the
> > celeron is at 100 finally.  Also, the cache shouldn't be the same - the
> > P III should have a considerable amount more, and I'm also assuming that
> > the P III has stuff like SSE, but I'm not sure.
> 
> OK.  It sounds like the difference between a PIII and Celeron IS the
> amount of L2 cache and the FSB speed.  That makes things a little clearer.
> 
> What is SSE?
> 
> --
> Cheers!
> 
> Randy
> 
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> Randy Arabie
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From: Sean Reifschneider <jafo at tummy.com>
To: clue-tech at clue.denver.co.us
Subject: Re: [CLUE-Tech] BCC'd email question
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On Sat, Feb 23, 2002 at 07:14:36PM -0700, Kevin Cullis wrote:
>Can a BCC'd email be grep'd, i.e. can you see who's been BCC'd by
>looking at the email file?

No, that's what the "B" in "BCC" means (Blind).  The BCC header is stripped
out of the message, and the mail server uses it to construct the envelope.
Remote mail servers do not necessarily know what other recipients are in
the bcc, and if they do, do not pass it on to the end user.

Sean
-- 
 Passionate hatred can give meaning and purpose to an empty life.
                 -- Eric Hoffer
Sean Reifschneider, Inimitably Superfluous <jafo at tummy.com>
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